Apple | Mobile |
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Business Dev & Design Entertainment | Social Media Tech Web Video |
Apple | Mobile |
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Business Dev & Design Entertainment | Social Media Tech Web Video |
Develops electronic design automation products.
Year Established: | 2004 |
Funding: | 610k |
Address: | Littleton, MA 01460 region: New England |
Telephone: | |
Mobile: | |
Fax: | |
Mail: | info@clkda.com |
Company URL: | http://www.clkda.com |
CLK Design Automation does not have any positions open at this time. However, we are always interested in receiving information from qualified candidates. If you feel you are an exceptional candidate for either of the positions listed below, please forward us your resume for possible future openings.
Development Positions:
Software developers with proven track records of achievement in the following areas:
Senior Developer positions require 5+ years of relevant experience; M.S. or Ph.D. in electrical engineering or computer science. Developer positions require 3+ years of relevant experience; M.S. or Ph.D. in EE or CS
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Field Application Engineer:
5+ years experience in ASIC or Custom semiconductor implementation or applications engineering. Must have excellent communication skills. Static Timing and signal integrity experience needed. Working knowledge of scripting tools such as TCL, Perl, Python. C level API experience a plus. B.S. or M.S. in EE or CS.
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Email your resume for Field Application Engineer Positions.
TSMCs 28-nm reference flow adds SiP solutions EE Times SAN FRANCISCOâLeading chip foundry Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) Wednesday (July 22) introduced its latest design reference flow said to extend the companys recommended design methodology to the 28-nanometer (nm) node. TSMCs Reference Flow 10.0 addresses new design challenges at 28-nm and includes innovations to enable system-in-package (SiP) design according to TSMC (Hsinchu Taiwan). New to the flow is an RTL-to-GDSII chip implementation track from Mentor Graphics Corp. TSMC said. Other EDA partners in the flow include Synopsys Inc. Cadence Design Systems Inc. and Magma Design Automation Inc. TSMC said as well as Altos Anova Apache Azuro CLK DA Extreme DA and Nannor. TSMC said it proactively engaged EDA ecosystem partners in creating the new methodology upon the introduction of its 28-nm process technology. For Reference Flow 10.0 TSMC said it went beyond physical verification of design rule checking (DRC) layout-versus-schematic (LVS) and extraction tools and engaged early collaboration with EDA partners to bring their place-and-route tools up to speed with the foundrys 28-nm process. Reference Flow 10.0 introduces SiP design solutions for the first time TSMC said. SiP solutions in the flow range from SiP package design electrical analysis of package extraction timing signal integrity IR drop and thermal to physical verification of DRC and LVS according to the company. New low-power features associated with Reference Flow 10.0 include support for pulsed latch a new low-power implementation scheme for power saving and hierarchical low power automation multi-corner power/timing co-optimization multi-corner low power clock tree synthesis vectorless power analysis and more enabling more effective power-aware implementation and power analysis TSMC said. To drive greater performance advanced stage-based on-chip variance optimization and analysis is made available for the first time enabling customers to get a more realistic look at timing for the purpose of removing redundant design margins TSMC said. The flow also includes a new electrical design-for-manufacturing (DFM) feature enabling customers to take into consideration the timing impact of silicon stress effects helping to increase yields TSMC said. TSMC Tuesday rolled out an interoperable custom IC design kit and two unified EDA data formats.
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Isadore Katz,President and CEO
Isadore has over 20 years of experience in executive management, marketing and product management in the EDA software and components industry. Most recently, Isadore was CEO and President of Lightchip, a supplier of component and software solutions to the telecommunications and cable industry. Prior to Lightchip, Isadore was CEO and President of Chrysalis Symbolic Design, an EDA software start-up selling to the semiconductor and electronics systems industry. Isadore grew the company to a $20m+ revenue ramp, and sold the company in 1999 to Avant! Isadore has held executive positions at Cadence Design Systems, MetaSoftware and Dataquest. He holds a Bachelor of Arts from Wesleyan University and Masters degree from the Sloan School at MIT.
Lee LaFrance,Vice President Engineering
Lee has more than 21 years of engineering and software development experience. Most recently, Lee was Director of Product Marketing for VCS at Synopsys, the market leader in simulation. Prior to Synopsys, Lee was Vice President of Engineering for Formal Verification at Avant!, where he led a 48-person team in the development of next-generation equivalence checking and model checking solutions. Lee has also held executive positions at Chrysalis and Cadence Design Systems, as well as engineering positions in processor development at Digital Equipment Corporation and Prime Computer. Lee holds a Bachelor of Science in Computer Systems Engineering from the University of Massachusetts.
Dr. Joao Geada,Chief Architect
Dr. Geada shares 15 years of EDA software experience. Most recently, Dr. Geada has been one of the lead architects in the verification and simulation group at Synopsys. Prior to Synopsys, Dr. Geada was a senior researcher at Cadence Design Systems and started his career at the IBM TJ Watson Research Center. Dr. Geada holds a PhD and Bachelor degree in Engineering from the University of Newcastle on Tyne (UK).